1. Field of the Invention
The present invention relates to the generation of pulses by means of a microprocessor. The present invention more specifically relates to the generation of variable width pulse trains, the respective widths of the pulses being programmable by means of a CPU of a microprocessor. Such pulse train generation is used, for example, in infrared remote controls for monitoring infrared-emitting diodes, the sequence according to which the pulse trains are generated and/or their number of pulses constituting a control code likely to be decoded by a detector of the transmitted infrared signals.
More generally, the present invention applies to the generation of variable width pulses, where the frequency of the pulses and the shape factor (width of a pulse for a period) of each pulse are programmable by means of a microprocessor.
2. Discussion of the Related Art
FIG. 1 shows, partially and in the form of a block-diagram, an example of a conventional implementation of a programmable pulse generator.
Such a generator includes a CPU 1 for executing an instruction program previously stored in a memory (not shown). CPU 1 conventionally is associated with a programmable counter (TIMER) 2 which can be used as a time base, especially for exchanges between the microprocessor and an external peripheral, for example, an infrared-emitting diode (not shown).
CPU 1 also is associated with a prescaler 3, the function of which is to receive an external clock CLKE and to generate to CPU 1 and timer 2 an operating clock CLK0. The counting frequency of timer 2 is lower than frequency CLK0. Prescaler PS 3 is programmable via a first register (PS-REG) 4 to set the division rate of external clock CLKE and, thus, the operating frequency of CPU 1.
Timer 2 is programmable, from CPU 1, via certain bits of register 4 and of a second register (T-REG) 5.
CPU 1 communicates with registers 4 and 5 via at least one address, data and control bus 9. Although not shown for the sake of clarity, bus(es) 9 is (are) also used to exchange information between CPU 1 and other conventional components of the microprocessor or associated thereto (for example, memories).
In addition to registers 4 and 5, timer 2 includes a digital counter 6, for example, based on flip-flops, the counting frequency of which is given by clock signal CLK0. Digital counter 6 is associated with a comparator 7 which compares the value issued by counter 6 with a threshold TH stored in register 5. An output signal OC of comparator 7 is sent to a clock input of an output flip-flop 8, the function of which is to transfer the state of a signal CB, present at the input of flip-flop 8 and issued by register 4, to an output of the flip-flop for each rising edge, for example, of signal OC. When threshold TH is reached, timer 2 positions output signal S of flip-flop 8 to a high or low state according to the state of bit CB.
Since timer 2 constitutes a time base for the microprocessor, counter 6 generally counts continuously. Obtaining an edge on output S generally consists of reading the counting value of counter 6, for example, contained in register 5, and then inputting into register 5 a counting threshold TH corresponding to a time differential between the time of the current edge and time for the occurrence of the next edge. For the needs of the present description, the time at which a new threshold TH is available for comparator 7 will be called the reset time of the digital counter 6.
FIG. 2 shows, in the form of timing diagrams, the operation of a pulse generator such as shown in FIG. 1. FIG. 2 shows an example of output signal S having a maximum frequency according to a clock signal CLK0 and to the occupation of bus 9.
The occurrence of a rising or falling edge of signal S must be preceded by a programming of registers 4 and 5 by means of CPU 1 which requires two programming cycles. First, threshold TH is programmed in register 5 (times t0 to t1) i.e., one programming cycle, then bit CB is programmed in register 4 (times t1 to t2), i.e., a second programming cycle. By t1, TH is available to comparator 7, and counter 6 is reset. However, threshold TH has to be large enough, such that an edge (for example, a rising edge) does not occur before time t2, because the control bit is not available in PS-REG until t2. Therefore, edge f1 (for example, the rising edge) of the output signal cannot be generated until t2 and thus output S remains in its former state. Similarly, a following edge f2 (for example, a falling edge) can only occur after two cycles of programming registers 4 and 5, respectively (times t2 to t3 and times t3 to t4).
The minimum interval between two successive edges of signal S, the minimum width of a pulse I, is conditioned by the time required to perform two cycles of programming (of registers 4 and 5) by CPU 1. In the example shown, it is assumed that six cycles of clock CLK0 are required to program a register. Thus, the minimum width of a pulse I is twelve cycles of clock CLK0 and the minimum interval between two successive pulses is also twelve clock cycles. Accordingly, in a conventional generator such as shown in FIG. 1, the minimum period of a pulse corresponds to four cycles of programming (of registers 4 and 5), which requires 24 cycles of clock CLK0. Also, when the pulse period is the minimum period, the shape factor of the pulses must be 50%.